(i) Field of the Invention
The present invention relates to a technique of forming a circuit pattern. More specifically, the present invention relates to a technique of forming a circuit pattern to which an electroless plating technique is applied.
(ii) Description of the Related Art
A method for forming a conductive circuit by giving electroless copper plating on a non-conductor to form a film thereon, covering areas where the conductive circuit is to be formed with an etching resist film and then removing areas other than the covered areas by etching is a conventional method in formation of a circuit pattern that is widely used in productions of a printed circuit board, components of a chip and the like.
At this time, in the electroless copper plating, a tin-palladium based catalyst is generally used. Since the tin-palladium based catalyst has excellent catalysis, it is widely used as a general catalyst in electroless plating with nickel or the like in addition to the copper plating. However, it is known that the advantages of the tin palladium based catalyst, i.e., its strong adhesion to a non-conductor and strong catalytic activity, turn into defects in some cases.
That is, when an electroless copper film (or a subsequent copper electroplated film) is deposited by the tin-palladium based catalyst and the copper film is then etched to form a circuit pattern, there is a defect that the catalyst remains on surfacial areas of the non-conductive layer which has become exposed as a result of dissolution of the copper film, so that insufficient insulation and a short between the circuits or other defect are liable to occur in the conductive circuit. Further, to improve reliability of soldered connection, the whole or a portion of the surface of the conductive circuit may be subjecting to electroless nickel plating as upper layer plating and then to gold plating. In such a case, there is a serious defect that a nickel plated deposit spreads onto the non-conductive layer other than the conductive circuit where the catalyst remains (off-pattern deposition). The above defects are not necessarily specific to production of a printed circuit board using the latest technology. However, they have been becoming particularly evident in recent boards which have a circuit pattern with a narrow pitch or whose copper film layer is made thin by a build-up process.
To overcome such a defect as insufficient insulation caused by the residual palladium catalyst or the spread of the upper-layer electroless nickel plated deposit in areas other than the circuit which is related to the residual palladium catalyst, a variety of proposals have been disclosed.
Firstly, a first method is intended for dissolving and removing the nucleus of the palladium catalyst on the surface of the exposed non-conductive layer primarily by a chemical process. For example, in Japanese Patent Application Laid-Open No. 339142/2001, a catalyst remover for a printed wiring board which comprises at least one of nitric acid, a chlorine ion, a nitrogen-containing heterocyclic compound, a polyhydric alcohol, a nonionic or cationic surfactant, an iron ion, urea or a derivative thereof, and at least one guanidine is disclosed. Japanese Patent Application Laid-Open No. 178752/2000 discloses a method for producing a multilayer printed board by a build-up construction method using a subtractive method or a semiadditive method, wherein, after formation of a conductive circuit by etching, removal of a palladium catalyst is carried out by use of a palladium catalyst remover for electroless plating which comprises an aqueous solution containing a nitrogen-containing aliphatic organic compound and an iodine-containing inorganic compound. Further, Japanese Patent Application Laid-Open No. 183522/2000 discloses a method for producing a multilayer printed wiring board having excellent electrical insulation reliability by etching an external copper foil layer to form a conductive circuit and then washing the surface of an exposed resin composition layer with nitric acid. Further, Japanese Patent Application Laid-Open No. 69632/1994 discloses a method for producing a printed wiring board which comprises the steps of carrying out a treatment with a palladium-tin solution, removing tin partially and then carrying out electroless plating, wherein, to remove tin, hydrochloric acid of 1 to 10N is adjusted to 10 to 80° C., and an adhesive layer is then treated with the hydrochloric acid for 0.5 to 30 minutes.
A method classified as a second method is a method comprising deactivating the nucleus of the adsorbed palladium catalyst. For example, Japanese Patent Application Laid-Open No. 236161/2000 discloses a method comprising the steps of forming a circuit pattern, immersing a board in an alkyl benzimidazole solution to form a protective film of the alkyl benzimidazole against a sulfide compound around the circuit pattern, then immersing the board in a palladium deactivator composed essentially of a sulfide compound to deactivate palladium as a catalyst, and then immersing the board in hydrochloric acid to remove the alkyl benzimidazole forming the protective film for the circuit pattern. Further, Japanese Patent Application Laid-Open No. 36652/2000 discloses a method for producing a printed wiring board in which a palladium catalyst remaining on the surface of an insulating layer is deactivated by use of a mixed solution of aqueous ammonia and a sulfide compound. In addition, Japanese Patent Application Laid-Open No. 36653/2000 discloses a method for producing a printed wiring board in which after formation of a circuit board, a palladium catalyst remaining on the surface of an insulating layer is deactivated by use of a diluted hydrochloric acid solution and a thiosulfuric acid compound solution.
A method classified as a third method is a method with some devices made on steps such as etching of a copper film and removal of a resin film. For example, Japanese Patent Application Laid-Open No. 190198/1998 discloses a method for producing a printed wiring board which comprises the steps of applying a plating catalyst including palladium on an insulating layer of a board having the insulating layer on a surface, then forming a first plated film, etching the first plated film so as to form a conductive circuit and forming a second plated film on the conductive circuit so as to produce the printed wiring board, wherein, after the surface of the board having the conductive circuit formed thereon by etching the first plated film is covered with an insulating resin, the surfacial insulating resin layer is removed such that the conductive circuit is exposed and areas other than the conductive circuit remain covered with the insulating resin, and then the second plated film is formed on the exposed conductive circuit. The above publication also discloses a method comprising irradiating the surfacial insulating resin layer with a laser beam as a method of removing the surfacial insulating resin layer. Further, Japanese Patent Application Laid-Open No. 186351/1996 discloses an oxidation treatment of the surface of a circuit board after etching of a copper layer. Illustrative examples of the oxidation treatment include a permanganic acid treatment, a plasma treatment and an ozone treatment. The above publication discloses a method in which the surface of the board excluding a photoresist layer is removed and palladium remaining on the surface of the board is also removed by the oxidation treatment. Japanese Patent Application Laid-Open No. 135918/1999 discloses a method comprising removing a catalyst remaining on the surface of an insulating layer by irradiating a formed circuit pattern with a laser beam. Japanese Patent Application Laid-Open No. 252622/2000 discloses a method for producing a printed wiring board in which an electroless plated film and catalyst nuclei in areas other than a lower conductive circuit are removed while the lower conductive circuit is treated with an etching solution containing a cupric complex and an organic acid in the co-presence of oxygen so as to form a roughened surface.
A method classified as a fourth method is a method with some device made on a catalyst for electroless plating. Japanese Patent Application Laid-Open No. 101054/1994 discloses a copper-based-raw-material-selective catalyst solution for electroless plating which comprises an aqueous solution containing (I) at least one of a nickel compound and a cobalt compound and (II) at least one thiourea. Japanese Patent Application Laid-Open No. 11448/1995 discloses a copper-based-raw-material-selective catalyst solution for electroless plating which comprises an aqueous solution containing (i) 0.0001 to 0.5 moles/L of palladium compound and (ii) 0.1 to 10 moles/L of at least one compound selected from an alkali metal halide, an alkali metal sulfate, an alkaline earth metal halide, an alkaline earth metal sulfate, an ammonium halide and ammonium sulfate. Japanese Patent Application Laid-Open No. 316612/1996 discloses a method for producing a printed wiring board in which a complex comprising a noble metal ion and an amino complexing agent is used as a catalyst nucleus and the amount of the catalyst nucleus added is controlled so as to satisfy a conditional expression in terms of noble metal. Further, 2-aminopyridine is disclosed as the amino complexing agent, and it is also disclosed that an alkaline solution containing a palladium ion and 2-aminopyridine is suitable as a catalyst-nucleus-containing treatment solution. Further, Japanese Patent Application Laid-Open No. 283951/1996 discloses a method of depositing palladium having a particle diameter of 0.01 to 0.05 μm by vacuum deposition or sputtering and explains that since the same level of catalytic performance can be attained only by a small amount of deposition, the amount of palladium to be deposited can be small, so that the amount of the catalyst remaining after etching can be reduced. Further, use of a catalyst other than palladium has also been studied. Japanese Patent Application Laid-Open No. 229280/1998 discloses a method for producing a printed wiring board which uses, as a catalyst solution for providing a catalyst for electroless plating, an aqueous solution containing at least one metal salt selected from a silver salt and a copper salt, an anionic surfactant and a reducing agent. Further, Japanese Patent Application Laid-Open No. 82878/2000 discloses a method for producing a build-up multilayer printed wiring board which comprises the steps of adsorbing a metal hydroxide colloid to the roughed surface of an insulating layer and the roughed internal surfaces of blind via holes, reducing the colloid to produce an active metal and then giving electroless plating thereon. As the metal hydroxide colloid, a mixed hydroxide colloid of excess nickel hydroxide and copper hydroxide is suitably used.
Patent Document 1
Japanese Patent Application Laid-Open No. 339142/2001
Patent Document 2
Japanese Patent Application Laid-Open No. 178752/2000
Patent Document 3
Japanese Patent Application Laid-Open No. 183522/2000
Patent Document 4
Japanese Patent Application Laid-Open No. 69632/1994
Patent Document 5
Japanese Patent Application Laid-Open No. 236161/2000
Patent Document 6
Japanese Patent Application Laid-Open No. 36652/2000
Patent Document 7
Japanese Patent Application Laid-Open No. 36653/2000
Patent Document 8
Japanese Patent Application Laid-Open No. 190198/1998
Patent Document 9
Japanese Patent Application Laid-Open No. 186351/1996
Patent Document 10
Japanese Patent Application Laid-Open No. 135918/1999
Patent Document 11
Japanese Patent Application Laid-Open No. 252622/2000
Patent Document 12
Japanese Patent Application Laid-Open No. 101054/1994
Patent Document 13
Japanese Patent Application Laid-Open No. 11448/1995
Patent Document 14
Japanese Patent Application Laid-Open No. 316612/1996
Patent Document 15
Japanese Patent Application Laid-Open No. 283951/1996
Patent Document 16
Japanese Patent Application Laid-Open No. 229280/1998
Patent Document 17
Japanese Patent Application Laid-Open No. 82878/2000